1. Field of the Invention
The present invention relates in general to integrated circuit (IC) manufacturing and, more specifically, to methods in IC manufacturing processes for sorting IC devices using identification (ID) codes, such as fuse ID's, in the devices.
2. State of the Art
Integrated circuits (IC's) are small electronic circuits formed on the surface of a wafer of semiconductor material, such as silicon, in an IC manufacturing process referred to as "fabrication." Once fabricated, IC's are electronically probed to evaluate a variety of their electronic characteristics, cut from the wafer on which they were formed into discrete IC dice or "chips," and then assembled for customer use using various well-known IC packaging techniques, including lead Frame packaging, Chip-On-Board (COB) packaging, and flip-chip packaging.
Before being shipped to customers, packaged IC's are generally tested to ensure they will function properly once shipped. Testing typically involves a variety of known test steps, such as pre-grade, burn-in, and final, which test IC's for defects and functionality and grade IC's for speed. As shown in FIG. 1, IC's that pass the described testing are generally shipped to customers, while IC's that fail the testing are typically rejected.
The testing standards for a particular IC product are sometimes relaxed as the product "matures" such that IC's previously rejected under strict testing standards may pass the relaxed testing standards. Consequently, reject bins containing previously rejected IC's are sometimes "culled" for IC's that are shippable under relaxed testing standards by testing the rejected IC's again using the relaxed testing standards. Unfortunately, while this "culling" process does retrieve shippable IC's from reject bins, it makes inefficient use of expensive and often limited testing resources by diverting those resources away from testing untested IC's in order to retest previously rejected IC's. Therefore, there is a need in the art for an improved method of "culling" or sorting such reject bins for shippable IC's.
Similarly, as shown in FIG. 2, all the IC's from the wafers in a wafer lot typically undergo enhanced reliability testing that is more extensive and strict than normal testing when any of the wafers in the lot are deemed to be unreliable because of fabrication or other process errors. Since a wafer lot typically consists of fifty or more wafers, many of the IC's that undergo the enhanced reliability testing do not require it because they come from wafers that are not deemed unreliable. Performing enhanced reliability testing on IC's that do not need it is inefficient because such testing is typically more time-consuming and uses more resources than normal testing. Therefore, there is a need in the art for a method of sorting IC's from a wafer lot into those IC's that require enhanced reliability testing and those that do not.
Likewise, as shown in FIG. 3, a new or special "recipe" for fabricating IC's on wafers is sometimes tested by fabricating some wafers from a wafer lot using the special recipe and other wafers from the wafer lot using a control recipe. IC's from the wafers then typically undergo separate assembly and test procedures so that the test results of IC's fabricated using the special recipe are not mixed with the test results of IC's fabricated using the control recipe, and vice versa. Test reports from the separate test procedures are then used to evaluate the special recipe and to determine whether the IC's are to be shipped to customers, reworked, repaired, retested, or rejected. Unfortunately, because the IC's undergo separate test and assembly procedures, undesirable variables, such as differences in assembly and test equipment, are introduced into the testing of the special recipe. It would be desirable, instead, to be able to assemble and test the IC's using the same assembly and test procedures, and to then sort the IC's and their test results into those IC's fabricated using the special recipe and those IC's fabricated using the control recipe. Therefore, there is a need in the art for a method of identifying individual IC's fabricated using a special or control recipe and sorting the IC's based on their fabrication recipe.
As described above, IC's are typically tested for various characteristics before being shipped to customers. For example, as shown in FIG. 4, IC's may be graded in test for speed and placed in various bins (e.g., 5 nanoseconds (ns), 6 ns, and 7 ns bins) according to their grading. If a customer subsequently requests a more stringent speed grade (e.g., 4 ns), IC's in one of the bins (e.g., a 5 ns bin) are re-tested and thereby sorted into IC's that meet the more stringent speed grade (e.g., 4 ns bin) and those that do not (e.g., 5 ns bin). While this conventional process sorts the IC's into separate speed grades, it makes inefficient use of expensive and often limited testing resources by diverting those resources away from testing untested IC's in order to retest previously tested IC's. Therefore, there is a need in the art for an improved method of "culling" or sorting bins for IC's that meet more stringent standards, such as a higher speed grading.
As described in U.S. Pat. Nos. 5,301,143, 5,294,812, and 5,103,166, some methods have been devised to electronically identify individual IC's. Such methods take place "off" the manufacturing line, and involve the use of electrically retrievable ID codes, such as so-called "fuse ID's," programmed into individual IC's to identify the IC's. The programming of a fuse ID typically involves selectively blowing an arrangement of fuses and anti-fuses in an IC so that when the fuses or anti-fuses are accessed, they output a selected ID code. Unfortunately, none of these methods addresses the problem of identifying and sorting IC's "on" a manufacturing line.